Microelectronic devices are used in computers, communications equipment, televisions and many other products. Typical microelectronic devices include processors, memory devices, field emission displays and other devices that have circuits with small, complex components. In current manufacturing processes, the components of such circuits are generally formed on a substrate or wafer with conductive, insulative and semiconductive materials. Each substrate typically has 50-200 microelectronic devices, and each microelectronic device may have several million components.
Because fabricating microelectronic devices generally involves forming electrical components at a number of layers and different locations, microelectronic devices generally have many conductive features to couple the various components together. Common conductive features in microelectronic devices include conductive lines formed in trenches in a dielectric layer (e.g., damascene lines) or interlayer contact plugs/vias formed in holes through a dielectric layer. Accordingly, the trenches for the conductive lines and the holes for the contact plugs are typically filled with aluminum, tungsten, copper, gold, silver, polysilicon or other suitable conductive materials.
One problem with conventional process for fabricating conductive features is that some of the conductive features may have defects that impact the performance of the resulting circuit. Conventional processes for filling contact holes or trenches with conductive materials typically involve covering a dielectric layer with a layer of conductive material, heating the conductive layer until it is deformable, and then applying pressure directly to the conductive layer to drive a portion of the conductive layer into the contact holes or trenches. Because the contact holes and trenches generally have a high aspect ratio (the ratio of height/width), small cracks often form in the conductive layer as it is deposited onto the dielectric layer. The existing cracks in the conductive layer often propagate as pressure is applied to the conductive layer and, if large enough, cause defects in the resulting conductive component. Thus, conductive components fabricated with conventional processes for filling contact holes or trenches may impair the performance of the resulting microelectronic devices.
Another problem with conventional processes for fabricating conductive features is that it is often time-consuming to prepare the substrate for subsequent processing. After the conductive material fills the contact holes or trenches, the substrate is typically planarized to the top of the underlying dielectric layer to electrically isolate the conductive features from one another and to provide a highly planar surface for accurately photopatterning additional layers of components. One desirable technique for planarizing substrates is chemical-mechanical planarization ("CMP") in which a substrate is moved across a polishing medium to remove material from the substrate. Although CMP processes produce a planar surface, they are time-consuming and require sophisticated equipment. Accordingly, it is generally desirable to planarize the surface without CMP processing, or to reduce the time required to planarize the surface with CMP processing.